IPrium releases BCH I.3 Coder/Decoder


TOMSK, Russia, November 20, 2012 - FPGA intellectual property (IP) provider IPrium LLC (www.iprium.com) has today announced that it has expanded its family of FEC IP products with a new BCH I.3 Codec IP Core for the G.975.1 "Forward error correction for high bit-rate DWDM submarine systems" standard. The BCH I.3 Codec IP Core is silicon-proven using multiple development boards and is fully compliant with ITU-T G.975.1 Standard (as of 02/2004) "Appendix I. Super FEC schemes I.3 Concatenated BCH super FEC code".

Pricing and Availability

The BCH I.3 Codec IP Core is available immediately in synthesizable Verilog or optimized netlist format, along with synthesis scripts, simulation test bench with expected results, and user manual. For further information, a product evaluation or pricing, please visit the IP Core page:

About IPrium LLC

IPrium Modem IP Cores allow designers of communication equipment to rapidly develop and verify their systems in a highly cost-effective manner. IPrium offers FPGA and ASIC IP Cores for high-quality modems to customers worldwide. Visit IPrium at www.iprium.com.

return