10G I.3 BCH Codec IP Core

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The IP Core implements the error-correcting coding I.3 Concatenated BCH super FEC codes for the ITU-T G.795.1 recommendation, supporting both continuous and burst modes. It is optimized for use with linear OTN OTU2 flow speed 10.7 Gbps fiber optic communications systems.

BCH(2040, 1930) inner decoder De-interleaver BCH(3860, 3824) outer decoder Interleaver

Version : 2.1
Build date : 2015.09
Ordering code : ip-i3-bch-codec
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel), ASIC (Digital ASIC)
The IP Core resource utilization and performance : Specification (PDF)