10G I.6 LDPC Codec IP Core

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FEC


IP Core implements the error-correcting coding I.6 LDPC super FEC code code for the ITU-T G.795.1 recommendation. Supports synchronous and batch mode. Optimized for use with linear OTN OTU2 flow speed 10.7 Gbps fiber optic communications systems.

Bit Demapping LDPC Decoder Bit Mapping

Version : 2.0
Build date : 2014.09
Ordering code : ip-i6-ldpc-codec
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel), ASIC (Digital ASIC)
The IP Core resource utilization and performance : Specification (PDF)

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