CCSDS AR4JA LDPC Encoder and Decoder IP Core

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The IP Core implements CCSDS AR4JA LDPC.

Key Features
  • Compliant with CCSDS 131.0-B-4 Standard, April 2022, TM synchronization and channel coding
  • Supports all 9 LDPC encoding schemes: rates 1/2, 2/3. 4/5 and block sizes 1K, 4K, 16K
  • Encoding rate up to 100 Mbit/s
  • Decoding rate up to 90 Mbit/s
  • On-the-fly block type change
  • Layered Min-Sum-Offset decoding with low implementation loss
  • Decoding early termination mechanism
  • Variable number of decoding iterations up to 256
Mem In Layered LDPC Processing Mem Out Control Message memory

Version : 1.0
Build date : 2022.11
Ordering code : ip-ccsds-ar4ja-ldpc-encoder-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)

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