FECs
The IP Core implements the decoding algorithm Viterbi, supporting both normal and trellis coding.
Version : 2.1
Build date : 2019.04
Ordering code : ip-viterbi-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel), ASIC (Digital ASIC)
The IP Core resource utilization and performance : Specification (PDF)
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