Viterbi Decoder IP Core

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Source code price : 7700 €
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The IP Core implements the decoding algorithm Viterbi, supporting both normal and trellis coding.

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Version : 2.0
Build date : 2014.09
Ordering code : ip-viterbi-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel), ASIC (Digital ASIC)
The IP Core resource utilization and performance : Specification (PDF)

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