FECs
The IP Core implements 100 Gbps Polar Code encoding and decoding.
Key Features:
- Fully customizable to any standard, including 3GPP 5G
- Successive-Cancellation algorithm
- Throughput up to 100 Gbits/s
- On-the-fly block type change
- Code block length (N) of 1024
- Payload length (K) from 100 to 1000
- Variable code rates from 1/10 to 9/10
- Variable "frozen bits" mask
Version : 1.0
Build date : 2022.12
Ordering code : ip-100-gbps-polar-encoder-decoder
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)
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