Modulators/Demodulators
The DVB-S Demodulator IP Core is a complete QPSK tuner with integrated DVB-S FEC Decoder. The IP Core includes a digital receiver, soft decision slicer, Viterbi decoder, deinterleaver, Reed-Solomon decoder, descrambler and a TS stream output FIFO.
Version : 1.1
Build date : 2016.08
Ordering code : ip-dvb-s-demodulator
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)
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