DVB-CID Demodulator IP Core

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The DVB-CID Receiver/Detector/Demodulator IP Core implements the modulation standard ETSI TS 103 129 V1.1.1 (2013-05) DVB-CID. The IP Core contains a Mixer, RRC Filter, Carrier/Timing Recovery block, Despreading and a BCH Decoder. The IP Core checks the CRC8 checksum and outputs the 2x61 bits message with CRC check result. The IP Core supports the blind scan mode to find the CID message in the interfering spectra.

The theoretical DVB-CID SNR (SNIR) for the ideal AWGN channel is -37.2 dB (BER = 1e-6). The IP Core implementation loss is 2.2 dB. The IP Core has BER = 1e-6 at SNR (SNIR) = -35.0 dB.

DVB-CID Demodulator IP Core

Version : 1.0
Build date : 2014.12
Ordering code : ip-dvb-cid-demodulator
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)