DVB-CID Demodulator IP Core

Netlist price : 15300 €
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The DVB-CID Receiver/Detector/Demodulator IP Core implements the modulation standard ETSI TS 103 129 V1.1.1 (2013-05) DVB-CID. The IP Core contains Mixer, RRC Filter, Carrier/Timing Recovery block, Despreading, BCH Decoder. The IP Core checks CRC8 checksum and outputs 2x61 bits message with CRC check result. The IP Core supports blind scan mode to find CID message in interfering spectra.

The theoretical DVB-CID SNR (SNIR) for ideal AWGN channel is -37.2 dB (BER = 1e-6). The IP Core implementation loss is 2.2 dB. The IP Core has BER = 1e-6 at SNR (SNIR) = -35.0 dB.

DDC with Mixer Resampler RRC Correlators Blind Search and Acquisition UW Detector Differential Decoder Slicer Descrambler BCH Decoder CRC Check Output FIFO

Version : 1.0
Build date : 2014.12
Ordering code : ip-dvb-cid-demodulator
Supported technologies : FPGA (Xilinx, Intel/Altera, Lattice, Microsemi/Actel)
The IP Core resource utilization and performance : Specification (PDF)